In traffic light controller which color is possible at a time in all four directions?
Green
Yellow
Red
Blue
Which pin is used to blank the display during digit switching in 8279 interface?
RD
WR
BD
DB
The DMA controller have access to how many channels at a time?
1
2
3
4
How many pins are in keyboard/display controller IC and DMA controller IC?
40,40
20,40
40,20
28,24
Which IC is used to perform parallel communication operation?
8251
8255
8254
8252
In 8255 how many ports available and that ports form how many groups?
2,2
3,2
2,3
3,3
In 8 channel-ADC interface how many address lines needed to operate the start of conversion channels?
1
2
3
4
In all 8086 interfacing concepts, which one of the address line is used as enable the decoder?
A0
A1
A2
A3
In 7 segment LED , is it possible to design all letters and characters?
Yes
No
In interrupt controller, in non-cascaded mode how many interrupts will be handled?
4
8
16
32
In DAC interface which address is used to enable DAC latch?
50H
60H
70H
78H
In ADC interface to enable start of conversion Which decoder input is given?
001
110
101
001
To write letter C in 7 segment LED, the hexa address is
34H
39H
45H
67H
To write letter C in LCD how many hexa address we need to calculate?
2
3
4
5
Which hexa address is used to select counter2 in 8254?
A4
B6
C7
A5
Which one is holding the current processing interrupt in 8259?
Priority resolver
In service register
Interrupt register
Comparator
In cascade connection of 8259 devices for master8259 and slave SP’/EN’ pin is connected in
Gnd and VCC
VCC and Gnd
4V,4V
4V,2V
In common anode type LED ,hexa code for letter H is
92H
89H
24H
42H
In 8255, BSR mode is ___________.
enabled by a ‘1’ in the MSB of control word
enabled by a ‘1’ in the LSB of control word
used to set/reset port B pins
used to set/reset port C pins
In a DMA write operation, the data is transferred _______.
from I/O to Memory
from Memory to I/O
from Primary memory to Secondary memory
from Secondary memory to Primary memory
A Square wave can be generated by operating the 8253 timer in ______.
Mode 0
Mode 1
Mode 3
Mode 5
In 8279, the keyboard entries are debounced and stored in ____________ that is further accessed by the CPU to read the key codes.
4 byte FIFO RAM
8 byte FIFO RAM
16 byte FIFO RAM
32 byte FIFO RAM
In Cascade mode, 8259 can handle _______.
upto 64 vectored priority interrupt
upto 60 vectored priority interrupt
upto 46 vectored priority interrupt
upto 40 vectored priority interrupt
In a Digital to Analog Converter, ________ refers to the smallest change in the analog output voltage for any change in the digital input.
Accuracy
Linearity
Resolution
Temperature sensitivity
In 8255, the control word to configure port A, B and C to configure as output port under I/O mode (Mode 0) operation is __________.
00H
10H
40H
80H
The control word value for configuring 8251 in asynchronous mode with 2 stop bits, odd parity and 8-bit character length with1xclock baud rate is ________.
0DH
10H
1DH
20H
The 8255 programmable peripheral interface is interfaced to a microprocessor to implement the following applications,
Interfacing an ADC to the microprocessor – the conversion is initiated by a signal from the 8255 on port C. A signal on Port C causes data to be strobed into Port A
Exchange data with another 8255. Port A works as a bidirectional data port supported by appropriate handshaking signals
Mode 0 for (I) and Mode 2 for (II)
Mode 2 for (I) and Mode 2 for (II)
Mode 1 for (I) and Mode 2 for (II)
Mode 2 for (I) and Mode 0 for (II)
The low active signals like DSR,DTR,CTS and RTS used in 8251 interface are called as,
Handshake signals
Universal signals
High Impedance signals
Modern signals
Illustrate the use of RS pin in LCD interface?
Reset select
Command/Data register select
Counter/timer select
Reverse the line select
The memory address of the last location of a 1KB memory chip is given as 0FBFF, Choose the address of the first location?
0F800H
0F801H
0F808H
0F817H
In 8251A, the pin that controls the rate at which the character is to be transmitted is
TXC (active low)
TXC (active high)
TXD (active low)
RXC (active low)
The registers that store the keyboard and display modes and operations programmed by CPU are
I/O control and data buffers
Control and timing registers
Return buffers
Display address registers
The sensor RAM acts as 8 byte first in first out RAM
Keyboard mode
Strobed input mode
Keyboard and Strobed input mode
Scanned sensor matrix mode
When a key is pressed, a debounce logic comes into operation in
Scanned keyboard special error mode
Scanned keyboard with N-Key rollover
Scanned keyboard mode with 2 key lockout
Sensor matrix mode
The data that is entered from the left side of the display unit is of
Left entry mode
Right entry mode
Left and Right entry mode
None of the mentioned
The FIFO status word is used to indicate the error in
Keyboard mode
Strobed mode
Keyboard and Strobed input mode
Scanned sensor matrix mode
The flag that increments automatically after each read or write operation to the display RAM is
IF
RF
AI
WF
The popular technique that is used in the integration of ADC chips is.
Successive approximation
Dual slope integration
Successive approximation and dual slope integration
None of the mentioned
The conversion delay in a successive approximation of an ADC 0808/0809 is.
100 milliseconds
100 microseconds
50 milliseconds
50 microseconds
The feature of mode 0 is
Any port can be used as input or output
Output ports are latched
Maximum of 4 Ports are available
All of the mentioned
What is correct range of frequency for 8257?
500Hz to 3 MHz
250Hz to 2 MHz
250Hz to 3 MHz
500Hz to 2 MHz
Which of the following is not true features of 8257?
It has three channels which can be used over three I/O devices
Each channel has 16 bit address and 14 bit counter
Each channel can transfer data up to 64kb.
Each channel can be programmed independently
Which mode allows 8/16-character multiplexed displays to be organized as dual 4 bit / single 8-bit display units?
Display Entry
Display Scan
Strobed Input
Scanned Keyboard Mode
What us true about Encoded Mode?
The unit contains registers to store the keyboard, display modes
The counter internally decodes the least significant 2 bits and provides a decoded 1 out of 4 scan on SL0-SL3
The processor is requested service only if any key is pressed, otherwise the CPU will continue with its main task.
The counter provides the binary count that is to be externally decoded to provide the scan lines for the keyboard and display.
In which mode, the CPU periodically reads an internal flag of 8279 to check whether any key is pressed or not with key pressure?
Interrupt Mode
Polled Mode
Decoded Mode
Encoded Mode
How many types of Interfacing?
2
3
4
5
The device that enables the microprocessor to read data from the external device is
Printer
Joystick
Display
Reader
The example of output device
CRT display
7 Segment Display
Printer
All of the Mentioned
The input and output operations are respectively similar to the operations.
Read, Read
Write, Write
Read, Write
Write, Read
The operation, IOWR (active low) performs.
Write Operation on input data
Write Operation on output data
Read Operation on input data
Read Operation on output data
The latch or IC74LS373 acts as
Good Input Port
Bad Input Port
Good Output Port
Bad Output Port
While performing read operation, one must take care that much current should not be.
Sourced from data lines
Sinked from data lines
Sourced or Sinked from data lines
Sinked from address lines
To avoid loading during read operation, the device used is.
Latch
Flipflop
Buffer
Tristate Buffer
The chip 74LS245 is
Bidirectional Buffer
8 bit input port
One that has 8 buffers
All of the Mentioned
In 74LS245, if DIR is 1, then the direction is from
Inputs to Outputs
Outputs to Inputs
Source to Sink
Sink to Source
In memory-mapped scheme devices are viewed as
Distinct I/O devices
Memory Locations
Only Input Devices
Only Output Devices
If the data transmission takes place in either direction, but at a time data may be transmitted only in one direction then, it is of
Simplex Mode
Duplex Mode
Semi Duplex Mode
Half Duplex Mode
TXD (Transmitted Data Output) pin carries serial stream of the transmitted data bits along with
Start Bit
Stop Bit
Parity Bit
All of the Mentioned
The signal that may be used either to interrupt the CPU or Polled by the CPU is
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